1. Field
An embodiment of the present invention relates to the field of integrated circuit design for test and more particularly, to scan design for double-edge-triggered flip-flops.
2. Discussion of Related Art
Scan chains including scan elements are frequently included in integrated circuits to provide the capability to control and observe internal states of the integrated circuit during testing or debug, for example.
For an integrated circuit device that implements scan capabilities there are typically two modes: a test mode and a functional mode. In the test mode, the internal state is configured into a scan chain that provides for control and/or observation of internal states. In the functional mode, the integrated circuit device operates according to specification (assuming a properly functioning part).
For a typical scan operation, an integrated circuit device is switched into a test or scan mode and the desired test data is scanned into the scan chain. The integrated circuit device is then switched into a functional mode and one or more functional clocks are applied. The device is then switched back into the scan mode to scan out captured values in order to observe the internal states of the device.
To provide for high controllability and observability, it is desirable to have a scan cell associated with each state element in an integrated circuit.